Field of the Invention
The present invention relates to a data transfer device and a data transfer method.
Description of Related Art
Conventionally, an imaging system such as a digital camera includes a plurality of large-scale integrations (LSI) to which various functional blocks are assigned. The plurality of LSIs are connected to a common bus for direct memory access (DMA). A plurality of functional blocks respectively assigned to the plurality of LSIs share one dynamic random access memory (DRAM) via a common bus. This type of imaging system includes a bus arbiter.
The bus arbiter controls the access to the DRAM by each functional block by adjusting and receiving DMA transfer requests of functional blocks accessing the DRAM. Specifically, the bus arbiter performs arbitration to preferentially receive DMA transfer requests of functional blocks responsible for high-priority processes while increasing the efficiency of use of the common bus as much as possible, for example, by reducing a band loss of the common bus occurring upon bank switching or a band loss of the common bus occurring upon switching between read and write operations.
Generally, according to the arbitration performed by the bus arbiter, when a high-priority functional block consecutively outputs DMA transfer requests, a situation may occur in which bus ownership does not pass to other functional blocks and processes of the other functional blocks are stagnated. A related-art technology for solving this problem is disclosed in Japanese Unexamined Patent Application, First Publication No. 2006-39672 1. According to the technology disclosed in the Japanese Unexamined Patent Application, First Publication No. 2006-39672 1, a high-priority functional block outputs DMA transfer requests at a constant time interval such that it is possible for the bus arbiter to receive DMA transfer requests of low-priority functional blocks even if there are consecutive DMA transfer requests of a high-priority functional block.